SoC Digital Verification Engineer, Multimedia Lab
6500 - 13000 SGDBYTEDANCE PTE. LTD.
About Us
Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more fun for people to connect with, consume, and create content.
Why Join ByteDance
Inspiring creativity is at the core of ByteDance's mission. Our innovative products are built to help people authentically express themselves, discover and connect – and our global, diverse teams make that possible. Together, we create value for our communities, inspire creativity and enrich life - a mission we work towards every day.
As ByteDancers, we strive to do great things with great people. We lead with curiosity, humility, and a desire to make impact in a rapidly growing tech company. By constantly iterating and fostering an "Always Day 1" mindset, we achieve meaningful breakthroughs for ourselves, our Company, and our users. When we create and grow together, the possibilities are limitless. Join us.
Diversity & Inclusion
ByteDance is committed to creating an inclusive space where employees are valued for their skills, experiences, and unique perspectives. Our platform connects people from across the globe and so does our workplace. At ByteDance, our mission is to inspire creativity and enrich life. To achieve that goal, we are committed to celebrating our diverse voices and to creating an environment that reflects the many communities we reach. We are passionate about this and hope you are too.
Job highlights
Positive team atmosphere, Career growth opportunity, Paid leave, 100+ mil users, Meals provided, Competitive compensation
Responsibilities
Team Introduction
Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Responsibilities
1. Verification Planning: Deeply analyze architecture and design specifications to develop comprehensive and high-coverage module-level, subsystem-level, or SoC system-level Test Plans.
2. Environment Development: Build from scratch or maintain highly reusable and automated advanced verification environments (Testbench) and components (Scoreboard, Monitor, Sequence, etc.) based on UVM methodology.
3. Test Execution & Closure: Develop high-quality testcases, execute Constrained Random and Directed tests, and drive Functional and Code Coverage to 100% closure.
4. System-Level Verification: Responsible for Gate-Level Simulation (GLS) and SDF back-annotated timing simulation. Assist in FPGA prototyping and Hardware/Software co-debugging on Emulation platforms (e.g., Palladium/ZeBu).
5. Flow Optimization: Develop and maintain regression testing scripts and automation tools to continuously improve the team's overall verification efficiency and compute resource utilization.
Qualifications
Minimum Qualifications:
1. Bachelor's degree or higher in Microelectronics, Computer Science, Electronic Communications, or a related field.
2. 3+ years of working experience in ASIC/SoC verification.
3. Mastery of SystemVerilog and UVM methodology, with the ability to independently build IP-level or SoC-level verification environments.
4. Proficiency in mainstream simulation and debugging tools (VCS/Incisive/Questa, Verdi, etc.).
5. Exceptional debugging and logical analysis skills; proficient in Python/Perl/Shell scripting for automation.
Preferred Qualifications:
1. Familiarity with the architecture, protocols, and complex data flows of core SoC subsystems (e.g., CPU/NPU clusters, Memory subsystems, NoC).
2. Hands-on experience with Hardware Emulation (Palladium, ZeBu) or FPGA prototyping platforms.
3. Proficiency in Formal Verification methodologies and tools (e.g., JasperGold).
4. Experience in SoC-level Performance and Power-Aware (PA) verification.
11250 - 22500 SGD
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