Principal Engineer / MTS, PDE Package Design
8500 - 16000 SGDMicron Semiconductor Asia Pte Ltd
Responsibilities
Own package architecture and execution from feasibility through tape-out, qualification, and production readiness, ensuring design intent is translated into manufacturable, reliable, and scalable solutions.
Serve as the technical authority for complex package issues, leading cross-functional reviews, trade-off decisions, and risk closure across product, silicon, technology, assembly, quality, supplier, and OSAT teams. Balance performance, reliability, manufacturability, cost, quality, and schedule to deliver production-ready solutions while mentoring engineers through difficult technical decisions.
Advance design rules, methodologies, automation workflows, and technology roadmaps for future products.
Represent the packaging team in Silicon–package–board co-design by integrating floorplan, interface, interconnect, power, signal, thermal, and mechanical requirements, and resolve cost and manufacturing trade-offs to achieve a balanced package solution.
Ability to apply baseline digital fluency and role-appropriate AI literacy to use AI-enabled tools responsibly and effectively for research, analysis, content creation, problem-solving, operational tasks, and achieving business outcome.
Requirements
Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Engineering, or a related discipline; PhD candidates are welcome to apply.
Minimum 10 years of relevant experience with deep expertise in package architecture and silicon–package co-design, including feasibility, stack-up, I/O and interconnect planning, substrate layout, routing, power delivery, signal return paths, and design verification.
Hands-on experience with multiple relevant package technologies and strong knowledge of manufacturability, assembly processes, substrates, materials, reliability, and failure mechanisms.
Proven ownership of complex package designs from feasibility and trade-off studies through NPI tape-out, qualification, and manufacturing handoff.
Advanced proficiency with Cadence Allegro Package Designer / SiP Layout or equivalent package-design tools, including design-rule and review workflows.
Strong technical leadership, mentoring, and stakeholder communication skills, with influence without direct authority; MTS candidates must demonstrate organization-wide impact on roadmaps, standards, or investment decisions.
Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements.
Contributes to a culture of continuous improvement by identifying, testing, and sharing AI-enabled enhancements within one’s scope of work
9000 - 16000 SGD
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