Average salary: SG$6,349 /monthly
More statsGet new jobs by email
6500 - 8500 SGD
...Experience in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure ~ Experience in using EDA tools from Cadence, Synopsys ~ Knowledge and working experience in one or more of the following: - Digital and mixed-signal design - USB interface...7000 - 14000 SGD
...following CAD Tools: Virtuoso Studio 23.1, Cadence ADE-L/XL, Maestro, Spectre, Virtuoso Layout, Quantus QRC, Voltus-XFi EMIR, EMX, and Synopsys Hspice, Primesim, StarRC, Quickcap, and Mentor Calibre/PERC Solid background in programming skills, circuit design, and device...8500 - 9500 SGD
...day operations of our global network and securityinfrastructures, supporting a highly distributed, international environment. Role Synopsis and profile As a Network & Security Expert within the Corporate IT Infrastructures team, you will: Design & operate network...7500 - 9000 SGD
...leading verification projects, using System Verilog and UVM verification methodology. ~ Proficient in using industry-standard EDA tools (Synopsys, Cadence). ~ Excellent analytical skills to diagnose complex issues and assess verification risk. ~ Strong communication skills...- ...Job Description: Role Synopsis The LNG Book within GPTI (Gas and Power Trading International) is responsible for optimising BP's advantaged LNG portfolio, including equity and third‑party supply, long‑term regasification and liquefaction contracts in the US and Europe...
bp
Singapore3 days ago 5500 - 10200 SGD
...for meeting specifications • MMMC optimization at Block and Sub-System Level • Timing closure with Crosstalk and AOCV / POCV • TCL scripting to fundamentally understand tool usage. MANDATORY EDA SKILLS • PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus...5000 - 10000 SGD
...verification using SystemVerilog/ UVM Strong understanding of verification process from test plan to coverage completion Strong communication and Analytical skills Understanding of HDL (Verilog, VHDL) Experience in using leading EDA software tools like Cadence/ Synopsys...13000 - 17000 SGD
...interactions as a plus. Strong programming or scripting skills (Python, C/C++, Perl, Java). Experience with industry EDA tools (Mentor, Synopsys, Cadence) is a plus. Leadership Demonstrated ability to act as a technical decision‑maker and mentor within the test...5000 - 7000 SGD
...integrity optimization, Amplifiers, reference voltages etc. · Experience in developing IC and proficient in design tools usage (Cadence/Synopsys, CustomCompiler/Fine Sim) For BMS · Good analytical skills and technical skills in analog/digital function circuits such as...5000 - 10000 SGD
...analysis, power and noise analysis and back-end verification across multiple projects. Proficient with backend design EDA tools, Synopsys ICC2 preferred Successfully track records of taping out complex SOC Working knowledge of deep sub-micron routing issues as they...5000 - 7000 SGD
...and placed products into volume production multiple times. Job Responsibilities: ~ Experienced in Cadence “Virtuoso VXL” and/or Synopsys “Custom Compiler” layout tools ~ Experienced in Mentor Graphics “Calibre” drc/lvs verification tool ~ Good problem-solving skills...- ...Job Description: Role Synopsis The Voyage Performance Specialist is a critical execution role within the Commercial Optimization team, responsible for safeguarding and maximizing voyage P&L through three integrated workstreams: navigation & routing compliance , vessel...
bp
Singapore25 days ago 6000 - 8000 SGD
...Experience in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure ~ Experience in using EDA tools from Cadence, Synopsys ~ Knowledge and working experience in one or more of the following: 1. Digital and mixed-signal design 2. USB interface...6000 - 8000 SGD
...~5 years or above experience in the area of layout design. ~ Knowledge in Electronic Design Automation (EDA) tools (e.g. Cadence, Synopsys, Mentor Graphic Calibre) ~ Knowledge in circuit reliability consideration for layout (e.g., ESD, latch-up, aging, EMIR) ~ Able to trouble...- ...Computer engineering with 7 years or more experience in a relevant field. 2. Familiarity with one or more VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, Spice Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity 3....
6000 - 8000 SGD
...planning, sensitive signal routing, current density and reliability considerations Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre) · Strong Communication skills, high level of independence, self-motivation and good team player...5000 SGD
...successful block-level delivery through to tape-out.Familiar with the complete ASIC/SoC front-end design flow and related tools (e.g., Synopsys/Cadence suite). # Preferred Qualifications: Experience in any of the following domains: CPU/GPU microarchitecture, high-speed...7000 - 15000 SGD
...Knowledge of low-power design techniques and power integrity issues is a plus. Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens. Excellent problem-solving skills and a strong team-oriented mindset. Effective communication skills and the...7000 - 9000 SGD
...leading verification projects, using System Verilog and UVM verification methodology ~ Proficient in using industry-standard EDA tools (Synopsys, Cadence) ~ Excellent analytical skills to diagnose complex issues and assess verification risk ~ Working experience from design...- ...Category Engineering Hire Type Employee Job ID 16434 Remote Eligible No Date Posted 03.18.2026 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving...
3500 - 8500 SGD
...of layout matching techniques (common centroid, interdigitation)Parasitic effects in high-speed designs ~ Hands-on experience with Synopsys Custom Compiler or Cadence Virtuoso (Layout XL / GXL)DRC/LVS tools (Mentor Calibre or equivalent) Good-to-Have: # Experience in...4000 SGD
...and proficiency in hardware description languages such as Verilog/VHDL is preferred.◦ Or familiarity with EDA tools such as Cadence, Synopsys, etc., is preferred.◦ Or proficiency in programming languages like C/C++, Python for algorithm development or automation scripting.◦...- ...ground surveillance Update the Security Department of incidents within 2 hours of occurrence via official mobile application group (Synopsis) Create Incident Report (HIR), Glitch Report, and record in Daily Occurrence Summary for all incidents Ensure all handing over...
4500 - 9500 SGD
...Signoff checks (DRC/LVS/ANT/ERC) and debugging ~ Timing closure collaboration with STA team ~ Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus. ~ Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet...5350 - 7500 SGD
...Responsibilities: 1. Study Design and Protocol Development (40%) Draft and refine clinical and translational protocols, including Synopsis, Study flow diagrams, Schedules of assessments (SoA), and biomarker sections Coordinate protocol input from PIs, Statisticians,...9000 - 13000 SGD
...TSMC or Samsung at either block-level or full-chip scale; ~ Proficient with industry-standard EDA tools, including Cadence and/or Synopsys platforms for P&R, STA, and physical verification; ~ Deep expertise across the full backend flow—from netlist to GDSII—including floorplanning...- ...Electrical Engineering, VLSI, or related field. ~4+ years of experience in ASIC physical design ~ Hands-on expertise in EDA tools: Synopsys (ICC2, Fusion Compiler, PrimeTime), ~ Cadence (Innovus, Tempus), or equivalent. ~ Strong background in timing analysis, low-power...
- ...including timing and power parameters, with the latest NAND ONFI interface standards Conducted simulation studies using Verilog and Synopsys VCS to support debug and design verification Implemented automation frameworks using C‑based programming, Python, and Perl to...
9000 - 12000 SGD
...regulations. ESSENTIAL DUTIES & RESPONSIBILITIES 1. Clinical Trials under Moleac Drug Development Program (50%) Develops study concept, synopsis, full protocol, Investigator’s Brochure (IB), Informed Consent Form (ICF) and periodic safety report. Contributes medical expertise...7500 - 10000 SGD
...solid hands-on experience in Digital Physical Design. Tool Proficiency: Proficient in PnR tools: Cadence Voltus/Innovus or Synopsys ICC2 . Familiarity with Physical Verification tools (e.g., Calibre ) and STA concepts is highly preferred. Attitude: Strong work...
