Average salary: SG$6,349 /monthly
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7500 - 11000 SGD
...for meeting specifications MMMC optimization at Block and Sub-System Level Timing closure with Crosstalk and AOCV / POCV TCL scripting to fundamentally understand tool usage. MANDATORY EDA SKILLS ~ PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus...7000 - 10000 SGD
...Expertise Languages :Verilog, System Verilog, C, C++. Verification Methodologies:UVM, OVM. Scripting Languages:Perl,C-shell. Simulators:Cadence IUS, Synopsys VCS, Verdi. Protocols:PCIe,AGPT,CFDM,SPI,ISO7816, DDR3, LPDDR2, GPIO, AXI, AHB, APB, JTAG, WDT, GPT....5000 - 7000 SGD
...Strong understanding of analog and/or digital IC design concepts Familiarity with industry-standard EDA tools (Cadence Virtuoso, Synopsys, Mentor, etc.) Experience or strong interest in scripting/programming (Python, SKILL, Tcl, or Perl) Good problem-solving skills,...9000 - 17000 SGD
...mesh planning, critical block placement, critical signal routing, matching and top-down integration flow. • Proficient in Cadence/Synopsys layout editor and physical verification tools; analytical and skillful in debugging physical verification such as DRC/LVS/ERC/ANT/PERC...4000 - 7000 SGD
...-integrated hardware development environments and engineering automation frameworks is preferred. Strong hands-on experience with Synopsys Fusion Compiler, Cadence Innovus, Synopsys PrimeTime and Cadence Conformal (LEC/CLP) Proficiency in TCL and Python scripting for workflow...6000 - 9000 SGD
...a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports Possess high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools Programming skills in any of the following are a plus: Skill or Ample or Perl, etc. Strong technical...9000 - 17000 SGD
...2 years of hands-on experience in physical design, including synthesis, PNR, STA, EMIR, and PV. ~ Strong expertise with EDA tools: Synopsys, Cadence, or Siemens (e.g., Design Compiler, IC Compiler, Fusion Compiler, Genus, Innovus, PrimeTime, Voltus, Calibre). ~ Proven track...5000 - 7000 SGD
...Requirements: Bachelor/Master Degree in Electrical/Computer Engineer. Experience in physical design with tape-outs. Knowledge of complete Netlist-to-GDS flow, Synopsys/Cadence tools like ICC2 or Innovus. Good in script programming with Perl, TCL/TK or other languages....5000 - 10000 SGD
...verification using SystemVerilog/ UVM Strong understanding of verification process from test plan to coverage completion Strong communication and Analytical skills Understanding of HDL (Verilog, VHDL) Experience in using leading EDA software tools like Cadence/ Synopsys...4500 - 5200 SGD
...digital and analog circuitry), and drove issue resolution with multi-functional teams Conducted simulation studies using Verilog and Synopsys VCS to support debug and design verification Implemented automation frameworks using C‑based programming, Python, and Perl to...5000 - 10000 SGD
...analysis, power and noise analysis and back-end verification across multiple projects. Proficient with backend design EDA tools, Synopsys ICC2 preferred Successfully track records of taping out complex SOC Working knowledge of deep sub-micron routing issues as they...6500 - 13000 SGD
...Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization. 5. Low Power Design: Participate in the...7000 - 12000 SGD
...PV), IR/EM analysis, STA, and SPICE simulation methodologies. Experience with industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, StarRC, Calibre, or equivalent. Understanding of PPAC trade-offs and optimization techniques....5500 - 9500 SGD
...Hands-on experience in physical design, including synthesis, PNR, STA, EMIR, and PV is a plus. Strong expertise with EDA tools: Synopsys, Cadence, or Siemens (e.g., Design Compiler, IC Compiler, Fusion Compiler, Genus, Innovus, PrimeTime, Voltus, Calibre). Proven track...8500 - 9500 SGD
...day operations of our global network and securityinfrastructures, supporting a highly distributed, international environment. Role Synopsis and profile As a Network & Security Expert within the Corporate IT Infrastructures team, you will: Design & operate network...4000 - 8000 SGD
...Verilog / System-Verilog - Digital design fundamentals (FSM, CDC, pipelining, timing) Experience with: - RTL simulation tools (Synopsys VCS / Cadence Xcelium) - Lint and CDC tools (SpyGlass / Jasper / Questa CDC) Preferred (Strong Advantage) Experience in high-speed...6500 - 8500 SGD
...Experience in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure ~ Experience in using EDA tools from Cadence, Synopsys ~ Knowledge and working experience in one or more of the following: - Digital and mixed-signal design - USB interface...4500 - 9500 SGD
...Signoff checks (DRC/LVS/ANT/ERC) and debugging ~ Timing closure collaboration with STA team ~ Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus. ~ Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet...7500 - 9000 SGD
...leading verification projects, using System Verilog and UVM verification methodology. ~ Proficient in using industry-standard EDA tools (Synopsys, Cadence). ~ Excellent analytical skills to diagnose complex issues and assess verification risk. ~ Strong communication skills...5350 - 7500 SGD
...Responsibilities: 1. Study Design and Protocol Development (40%) Draft and refine clinical and translational protocols, including Synopsis, Study flow diagrams, Schedules of assessments (SoA), and biomarker sections Coordinate protocol input from PIs, Statisticians,...- ...Electrical Engineering, VLSI, or related field. ~4+ years of experience in ASIC physical design ~ Hands-on expertise in EDA tools: Synopsys (ICC2, Fusion Compiler, PrimeTime), ~ Cadence (Innovus, Tempus), or equivalent. ~ Strong background in timing analysis, low-power...
9000 - 12000 SGD
...regulations. ESSENTIAL DUTIES & RESPONSIBILITIES 1. Clinical Trials under Moleac Drug Development Program (50%) Develops study concept, synopsis, full protocol, Investigator’s Brochure (IB), Informed Consent Form (ICF) and periodic safety report. Contributes medical expertise...- ...Category Engineering Hire Type Employee Job ID 16434 Remote Eligible No Date Posted 03.18.2026 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving...
- ...commercialization ~ Strong expertise with photonic simulation and EDA environments such as; COMSOL, Ansys, RSoft, Cadence Virtuoso, Synopsys OptoCompiler, Luceda IPKISS, Similar photonic design platforms ~ Experience designing advanced photonic components including; High-...Remote job
- ...verification methodology. Experienced with Linux OS and front-end EDA tools such as Spyglass, Design Compiler (DC), PrimeTime (PT), VCS from Synopsys/Cadence/Mentor. Skilled in scripting languages such as Tcl, Perl, Python. Strong logical thinking, communication, and teamwork...
5000 - 9000 SGD
...Utilize CMOS analog design fundamentals to create efficient and scalable analog circuit components. Operate Cadence Virtuoso or Synopsys Custom Compiler environments to perform custom IC design and layout tasks. Conduct circuit simulations and verification using HSPICE...- Role Synopsis The LNG Book within GPTI (Gas and Power Trading International) is responsible for optimising BP's advantaged LNG portfolio, including equity and third‑party supply, long‑term regasification and liquefaction contracts in the US and Europe, a global customer base...
PKO BP
Singapore18 days ago - ...related field. # Familiar with IC DFT, IC logic design flows, or IC verification flows # Proficient in using relevant EDA tools from Synopsys or Mentor.; # Possess proficient scripting skills (such as TCL/Perl/Python, etc.) Interested candidates, who wish to apply...
persol apac
Singapore17 days ago - ...Computer engineering with 7 years or more experience in a relevant field. Familiarity with one or more VLSI design tools (Cadence, Synopsys, Mentor & Ansys) for Place & Route, Spice Simulation, DRC/LVS Physical Verification, Static Timing Analysis and Power Integrity...
Broadcom
Yishun8 days ago - ...a high level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports Possess high-level proficiency/knowledge of Synopsys or CADENCE layout entry tools Programming skills in any of the following are a plus: Skill or Ample or Perl, etc. Strong technical...
Marvell Technology - Multimedia Solutions Business
Singapore16 days ago
